To address the reductions in design ground rules that typically accompany state-of-the-art methods of forming highly integrated circuit devices (e.g., memory devices), self-alignment techniques have been developed to address limitations associated with conventional optical photolithography techniques. A conventional method of forming integrated circuit memory devices using self-alignment techniques is illustrated by FIGS. 1A-1C. In particular, FIG. 1A illustrates the steps of forming device isolation regions 2 (e.g., shallow trench isolation (STI) regions) in a semiconductor substrate 1 and then forming a gate oxide layer (not shown) on a face of the substrate 1. A plurality of gate lines 8 are then formed on the gate oxide layer. The gate lines 8 may be formed by depositing a polycrystalline silicon layer 4 on the gate oxide layer and then depositing a polycide layer 5 (e.g., WSi.sub.2 or TiSi.sub.2) on the polycrystalline silicon layer 4. A gate mask layer 6 (e.g., silicon nitride layer) is then formed on the polycide layer 5. Conventional photolithographically defined masking and etching steps are then performed to etch the plurality of layers and define a plurality of gate lines 8. Dopants are then implanted into the substrate 1 to define an impurity region 9a in the cell array region, and define a plurality of shallow source/drain regions 9b and 9c in the peripheral circuit region, using the gate lines 8 as an implant mask. Silicon nitride spacers 10 are then formed on sidewalls of the gate lines 8. N-type dopants are then selectively implanted into the peripheral circuit region to define self-aligned N-type source and drain regions 11a therein. Steps are also performed to selectively implant P-type dopants into the peripheral circuit region to define self-aligned P-type source and drain regions 11b therein. A first interlayer insulating layer 12 (e.g., oxide layer) may then be formed on the substrate 1, as illustrated, and then planarized using conventional chemical-mechanical polishing (CMP) or etch-back techniques.
Referring now to FIG. 1B, a self-aligned contact hole 14 is then formed in the first interlayer insulating 12, by etching the first interlayer insulating layer 12 to expose the impurity region 9a. During this etching step, an etchant is used that preferably etches the first interlayer insulating layer 12 at a high rate relative to the rate at which the spacers 10 and gate mask layer 6 are etched. A conductive plug 16 is then formed in the contact hole 14 using conventional techniques. Unfortunately, although the silicon nitride spacers 10 and gate mask layer 6 may act to prevent the formation of a short circuit between the polycide layer 5 and the conductive plug 16, the steps to form the contact hole 14 may cause the impurity region 9a to become overetched, as highlighted by region 17. The steps to define the silicon nitride spacers 10 may also result in some degree of overetching of the impurity region 9a. Such overetching may increase the resistance of the contact formed between the impurity region 9a and the conductive plug 16 and may reduce the reliability of memory devices formed in the cell array region (e.g., may increase refresh failure rate). To address these problems, plug ion implantation steps are typically performed to improve contact resistance and thin oxide layers may be formed on the impurity regions 9a to repair etching damage.
Referring now to FIG. 1C, a second interlayer insulating layer 20 is then deposited on the first interlayer insulating layer 12. Selected portions of the gate mask layer 6, the first interlayer insulating layer 12 and the second interlayer insulating layer 20 are then etched to define a plurality of contact holes 21a-21e. However, such etching steps may cause the polycide layer 5 and the source/drain regions 11a and 11b to become overetched if the contact holes are etched simultaneously, as illustrated by highlighted region 24. Etching the contact holes 21a-21e simultaneously may also be difficult since the formation of each contact hole may require a different material to be etched. For example, to define contact hole 21a, only the second interlayer insulating layer 20 needs to be etched, however, to define contact holes 21b and 21d, the first and second interlayer insulating layers must be etched in addition to the silicon nitride gate mask layer 6. These contact holes 21a-21e may then be filled with a conductive material (e.g., metal) to define a plurality of contacts 22a-22e.
To inhibit the occurrence of over-etching defects, a thin silicon nitride layer can be deposited on the substrate and gate lines 8 after the source and drain regions have been formed. However, if the silicon nitride layer has an uneven thickness (e.g., thicker on top of the gate lines 8 and thinner on the source and drain regions 11a and 11b), overetching of the source and drain regions may still occur because silicon typically does not have good etching selectivity relative to silicon nitride.
Another conventional method of forming integrated circuit memory devices using self-alignment techniques is illustrated by FIGS. 2A-2B. In particular, FIG. 2A illustrates the steps of forming device isolation regions 32 in a semiconductor substrate 30 and then forming a gate oxide layer (not shown) on a face of the substrate 30. A plurality of gate lines 38 are then formed on the gate oxide layer. The gate lines 38 may be formed by depositing a polycrystalline silicon layer 34 on the gate oxide layer and then depositing a polycide layer 35 (e.g., WSi.sub.2 or TiSi.sub.2) on the polycrystalline silicon layer 34. A gate mask layer 36 (e.g., silicon nitride layer) is then formed on the polycide layer 35. Conventional photolithographically defined masking and etching steps are then performed to etch the plurality of layers and define a plurality of gate lines 38. Dopants are then implanted into the substrate 30 to define an impurity region 39a, and a plurality of shallow source/drain regions 39b and 39c, using the gate lines 38 as an implant mask. To enhance the electrical characteristics of silicide contact layers 46 to be formed during subsequent process steps (by reducing substrate damage), a thin oxide layer 40 is then formed on the substrate 30 and on the sidewalls of the gate lines 38, as illustrated.
Next, silicon nitride spacers 42 are then formed on sidewalls of the gate lines 38 using conventional techniques. Steps are then performed to selectively implant N-type dopants into the peripheral circuit region to define self-aligned N-type source and drain regions 44 therein. Steps are also performed to selectively implant P-type dopants into the peripheral circuit region to define self-aligned P-type source and drain regions 45 therein. Highly conductive silicide contact layers 46 are then formed on the source and drain regions 44 and 45 using conventional techniques. A first interlayer insulating layer 48 (e.g., oxide layer) may then be formed on the substrate 30, as illustrated, and then planarized using conventional chemical-mechanical polishing (CMP) or etch-back techniques.
A self-aligned contact hole 49 is then formed in the first interlayer insulating 12, by etching the first interlayer insulating layer 48 to expose the impurity region 39a. During this etching step, an etchant is used that preferably etches the first interlayer insulating layer 48 at a high rate relative to the rate at which the spacers 42 and gate mask layer 36 are etched. However, during this etching step, the portions of the thin oxide layer 40 that extend between the gate lines 38 and the silicon nitride spacers 42 may become excessively etched, as illustrated by highlighted region 50. Such over etching may expose the polycide layers 35. Then, during formation of a conductive plug 52 in the contact hole 49, a parasitic short circuit may be formed between the conductive plug 52 and the polycide layer 35.
Referring now to FIG. 2B, a second interlayer insulating layer 54 is then formed on the first interlayer insulating layer 48. Contact holes 55a-55e are then formed and filled with contacts 56a-56e, as illustrated. Unfortunately, the formation of such contact holes may cause the silicide contact layers 46 to become overetched, as illustrated by highlighted region 58. Such overetching may reduce device reliability by, among other things, increasing contact resistance and junction damage.
Thus, notwithstanding the above-described methods illustrated by FIGS. 1A-1C and 2A-2B, there continues to be a need for improved methods of forming integrated circuit devices that increase reliability by reducing the likelihood of parasitic over-etching.